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Programmed-Via Placement Pattern

IP.com Disclosure Number: IPCOM000043431D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Linsker, R [+details]

Abstract

In electronic device wiring packages presently using programmed-via sites around which wiring is deflected ('jogged'), the jogs increase wire length and can reduce yield by increasing the number of bendpoints. Such jogs can be eliminated by placing the via sites at different relative positions within different 'cells' of the wiring grid. An advantage is that the disclosed pattern avoids the reduced wirability that can result from other types of in-line via patterns. Consider an electronic wiring package with k wiring tracks per channel in both horizontal and vertical directions, where a channel is a horizontal or vertical swathe bounded by pins or other blockages, where a 'cell' is the rectangle defined by adjacent pins or blockages, and where to improve wirability one programmed-via (PV) is required per cell.