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Bit Substitution for Refresh of Systems With Unequal Memory and Bus Widths

IP.com Disclosure Number: IPCOM000043437D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Livingston, DL Sucher, DJ Walk, BM [+details]

Abstract

In dynamic-random access memories (DRAMs), a periodic refresh is necessary to prevent loss of data due to charge leakage of the dynamic storage cells. On modern DRAMs, this refresh is accomplished by delivering a row address strobe (RAS) to a fixed set of row addresses over a predetermined time period. In some computer systems, there is an inequality between the width of the memory subsystem and the width of the data block which is addressable by the system bus. This unequal memory/bus width station might arise, for example, in a system in which a high performance guest processor/memory combination is attached to a lower performance host system, in which case the width of the memory subsystem is greater than the width of the system bus.