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Video Signal Processing Circuit Disclosure Number: IPCOM000043447D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04

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Kobayashi, Y [+details]


This article describes a video signal processing circuit in which threshold voltages applied to comparator circuits are produced by a combination of peak hold circuit and resistor ladder circuit. Referring to Fig. 1, a video signal is generated by a CCD (charge-coupled device) array of a document scan station (not shown).