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High Speed Comparator Circuit

IP.com Disclosure Number: IPCOM000043452D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Chang, PT Dickol, JE [+details]

Abstract

A high speed comparator circuit for high performance array test systems is provided. Typical comparator circuits will not operate beyond 200 MHz. As shown in the figure, the first stage is a high gain differential cascode amplifier 1 with outputs clamped by Schottky diodes 3 and 5. The high gain with clamped outputs minimizes change in propagation delay for varying input overdrives. The second stage 7 is a simple emitter coupled amplifier which boosts the output of the first stage from 400 mV (peak to peak) to 1.2 V (peak to peak). This stage is necessary to provide sufficient drive for the output stage. The output stage 9 is a conventional Schottky diode differential amplifier typically employing 5 GHz pnp transistor devices rather than npn transistor devices.