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Browse Prior Art Database

PARITY Checker/Generator

IP.com Disclosure Number: IPCOM000043467D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Torres, A [+details]

Abstract

Parity checking of data in microprocessor storage channels typically requires a number of logic levels. The invention described in this article represents a method for generating a parity error signal for 36 bits utilizing only four logic levels and possibly only three logic levels (depending on polarity configuration). Parity Checking Requirements A major requirement imposed on the design of logic for microprocessor address and data channels is to check or generate parity on all four bytes of data plus the Tag logic, and to respond with the correct combination of ACK and NACK signals. This process typically requires a number of logic levels.