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High Performance, High Density Capacitively Loaded FET Static RAM

IP.com Disclosure Number: IPCOM000043496D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04

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Wang, W [+details]


The use of a gate capacitor in series with a resistor as an RC filter to reduce soft errors can not only increase cell size but also increases write time delay over a conventional six-device, poly-loaded static RAM (random-access memory). However, by using a thin film capacitor between metal ground and second-level polysilicon, one can eliminate soft errors in a capacitively loaded FET static RAM while cell size and write time delay are kept the same as with conventional six-device static RAMs. The cell circuit configuration is shown in Fig. 1, and the cell layout with stack capacitor is shown in Figs. 2A and 2B. The stack capacitor is formed between metal tied to ground potential and second level polysilicon, as shown in Fig. 3. The capacitor improves transient read stability in the static RAM.