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Embedded Random-Access Memory Features Improving Test Data Generation

IP.com Disclosure Number: IPCOM000043513D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04

Publishing Venue

IBM

Related People

Authors:
Omet, D [+details]

Abstract

This proposal relates to the test of the control lines which drive a random-access memory (RAM) embedded in a gate array chip, without the need of specific hardware (master-slave shift register latch). This is done by using the circuits already used for testing the memory in AC mode and adding a selector circuit. The RAM is a 2 x 32 x 36 position memory arrangement. Its operation is controlled by means of ten control lines: one read/write (RW) line for each memory and four write select (WS) lines for each memory. The circuits shown within the dotted line box are added to perform the test function. The eight WS lines are connected to an 8-way selector which is driven by a 1-out-of-8 decoder. This decoder is needed for testing purposes. This reduces the number of output pads needed to measure the AC performance of the RAMs.