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Dot-Able Frequency Generator

IP.com Disclosure Number: IPCOM000043549D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

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Gray, KS Lewis, SC [+details]


A refresh cycle start circuit for a dynamic RAM (random-access memory) particularly adapted for use in low power battery back-up situations is illustrated in Figs. 1 and 2. In standby, transistor 11 is on, holding down node B and the 10 mA current source. The external capacitor C1 is discharged by the external resistor R1. This discharge rate provides the refresh interval desired. When transistor 11 turns off, node B rises, pulling OC completely to ground. This guarantees that all chips using the same RC will be triggered. Node B also pre-charges the low power start buffer and starts the 100 mA pulsed current source I1. Since transistor 10 is now on hard, OC remains at ground. A 4 msec delay allows node B to rise completely before being pulled back to ground.