Browse Prior Art Database

Nitride/Polyimide Isolation Enhancement

IP.com Disclosure Number: IPCOM000043561D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Leipold, WC Motsiff, WT Rath, PC [+details]

Abstract

In this enhanced process for fabricating dual-dielectric nitride/polyimide passivated IGFET devices the silicon nitride layer is made much thinner than it is in conventional devices of this type and is entirely covered by a thin polyimide layer that is formed prior to the formation of the usual thicker polyimide layer, which only partially overlies the nitride layer. The composite nitride/polyimide layer is much less susceptible to stress cracking and the effects of pinholes, cusps and foreign materials than the conventional thicker nitride layer. The occurrence of metal-to-metal vertical shorts and the amount of interlevel metal-to-metal capacitance are greatly reduced. The structures produced by the old and new processes are contrasted in Figs. 1 and 2.