Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
A method is described for testing semiconductor memory chips. By means of this method, errors attributable to a slight asymmetry of the two half cells of a memory cell and errors attributable to other causes can be rapidly and reliably distinguished from each other. The figure is a detailed view of semiconductor chip cells arranged in the form of a matrix. This view shows twelve memory cells with two half cells each. In memory, the bit line pairs of each column are crossed twice to compensate for asymmetries of the bit-line capacitances. For layout reasons, two adjacent bit line pairs are mirrored. It is assumed that symmetry errors have occurred in the hatched half cells of the twelve illustrated memory cells, so that their read signal is weak compared with that supplied by the non-erroneous half cells.