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Parallel/Sequential Parity Bit Generator for a Counter Disclosure Number: IPCOM000043575D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

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D'Hervilly, G De La Salle, C [+details]


The usual way to implement a parity bit generator, on a data bus, can be greatly improved in terms of area and/or delay, as the result can be predicted from the previous data bus value. In a very general manner, a truth table is built which defines whether the parity bit will change the next cycle time or not, depending on: - the present bus state, and - the forthcoming control bus state which will modify the present bus state. Hence, the parity bit computation can take place during the incrementation time itself. This method has been applied to an incrementing 8-bit counter: - The parity generator area-delay product is roughly divided by 2. - Last but not least, the parity generation does not impact the total cycle time.