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Browse Prior Art Database

Double Precision Multiply Operation

IP.com Disclosure Number: IPCOM000043587D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Beraud, JP [+details]

Abstract

This article describes how to perform a double precision multiplication using a single precision multiplier and a double precision arithmetic logic unit (ALU). A simple extra logic performs an efficient multiplexing of a double precision ALU. With a 4 x 4 multiplier which works in twos complement and in sign/magnitude, it is possible to perform an 8 x 8 multiplication using the following rules: A is a twos complement word of 8 bits. A = - 27a7 + 26a6 + 25a5 + 24a4 + 23a3 + 22a2 + 21a1 + 20a0 A = 24 (-23a7 + 22a6 + 21a5 + 20a4) + (23a3 + 22a2 + 21a1 + 20a0) A = 24 B + C If D is another word, D = 24E + F. Thus the product A x D is equal to: 28 (B.E) + 24 (B.F) + 24 (C.E) + (C.F) The 8 x 8 bit multiplication is decomposed into four multiplications plus three additions made after appropriate shifting.