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Simplified LSSD Clock Generator

IP.com Disclosure Number: IPCOM000043623D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

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Bersac, JM Orengo, G [+details]


This article describes a circuit which generates the clocking of logic circuits in a LSSD (Level Sensitive Scan Design) environment. Functional and test modes of clocking are possible. This clock generator is comprised of three parts: - a phase generator comprising two JK flip-flops 1 and 2 whose respective outputs Q1 and Q2 are two phases øA and B with a 90 shift in phase, - a selection circuit which allows two types of input clocks: test clocks (LSSD type) or functional phases A and ø B. The outputs of the selection circuit feed the decode circuit, - a decode circuit, transparent for LSSD clocks, which converts phases into pulses. Then the outputs of the decode circuit are always LSSD clocks.