Memory Decode Architecture
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Memory decode architecture is described for data processing systems having pipelined addressing bus cycles, such as the Intel 80286 processor, which maximizes the cycle time performance of memory or I/O. The timing of the address outputs is pipelined from the bus interface unit of the Intel 80286 processor chip. This allows as much time as possible for the data access. The timing of the address outputs is pipelined such that the address of the next bus operation becomes available during the current bus operation. Address decode and routing logic can operate in advance of the next bus operation. As shown in the figure, the local address signals LA17 through LA23 were added to the I/O channel, to take advantage of the pipelined addressing of the Intel 80286 for memory address.