The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Latch Oscillator

IP.com Disclosure Number: IPCOM000043690D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue


Related People

Pollmann, K Remshardt, R Schettler, H Zuehlke, R [+details]


The stage delay of latches can be determined by the circuit of Fig. 1. This circuit is a ring oscillator built from the latches 1 to n and the logic circuits CD1, CS1 to CDn, CSn, INV1. The oscillator frequency depends on the number of stages in the loop. The contribution of the latches to this frequency is determined by comparison with a reference oscillator containing all the stages of the oscillator loop except for the latches. The frequency shift related to the latches is easily converted into the stage delay. The latch ring oscillator oscillates only if the loop includes a clock shaper CS, the circuit diagram of which is shown as an example in Fig. 3. The output of CS is amplified by a clock driver CD consisting of two inverters (Fig. 2). As shown in Fig.