Stackable Plastic Semiconductor Chip Carrier
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
A stackable plastic semiconductor chip carrier is provided. Alignment is assured by molded bosses on the top surface of the bottom carrier which mate with molded holes in the bottom surface of the top carrier. Peripheral leads are placed so that they align when the carriers are snapped together. The bottom carrier 1, as shown in Fig. 2, is molded with four bosses 3 on the top surface. The top carrier 5, as shown in Fig. 1, is molded with four holes 7 on centers, the same as the four bosses. Each carrier is provided with an appropriate number of leads 9 disposed in an identical pattern around the periphery of the carrier. After a semiconductor chip is mounted within each carrier, the carriers are snapped together. This aligns the leads from the top and bottom carriers.