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Asynchronous Interface Tester

IP.com Disclosure Number: IPCOM000043728D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

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Related People

Bogholtz, R Bosch, L Kazmierczak, G Mezzacappa, V Perini, G [+details]


The increasing complexity of large memory systems requires a greater number of control lines, more critical timings and the presence of more states and sequential paths than formerly permitted in the simple store/fetch stage of previous memories. To cope with these complications, memory BSMs (basic storage modules) with allowable simultaneous Read and Write data transfers (done asynchronously) require a detailed interface specification. This specification details all pulse requirements for Read, Write, Refresh and the limits imposed on access, cycle, overlap, etc. The BSM is guaranteed to work properly if the specification is followed. Despite this precaution, the case may arise when the specification is not being met by the system, but when the occurrence of this failure is too infrequent to be seen by the oscilloscope.