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Error Correction for Block Transfer Storage Disclosure Number: IPCOM000043730D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

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Related People

Ryan, PM [+details]


Block transfer memory systems, because of their size (109-1010 bytes), pose a particular problem in the correction of multiple errors. Such memories are organized to provide several thousand bytes of data in consecutive words from consecutive cells of one or more error correcting code (ECC)-related array chips for each request for a block transfer. Individual faults occurring from time to time in the array chips can cause errors in the stream of ECC words in some of the blocks. As long as no word contains more errors than can be corrected in-line by the ECC logic, each block transfer is correctly completed in one pass through the sequence of consecutive addresses.