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Test Logic for Computer Attachment Cards

IP.com Disclosure Number: IPCOM000043740D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Baker, RG Lin, HC Taylo, JD [+details]

Abstract

The illustrated circuit arrangement facilitates the testing of I/O attachments to personal computer-type systems. Sets of latches added to the I/O controller attachment cards and gating paths between the latches and the computer system bus permit the computer system to obtain latched readings of address and data signals appearing on the card for diagnostic evaluation. As distinct from the conventional diagnostic technique of exercising the card and reading its signals in synchronism with operations of diagnostic programming facilities in the computer system, the present latching technique allows the attachment subsystem to capture the test information and present it to the computer system asynchronously.