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High Speed Programmable Clock Generator

IP.com Disclosure Number: IPCOM000043753D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Koennecker, OH [+details]

Abstract

This programmable clock employs a free-running counter 10 that does not have to be reset, thereby allowing the clock generator to operate at higher frequencies than are possible in clock generators where such resetting occurs. A binary number representative of the desired clock frequency is entered into offset register 14. This number is transmitted to the output of latch 12 where it is compared by comparator 16 with the count of the counter 10, which driven in free-running mode by crystal oscillator 18. When the compare occurs, the comparator generates a compare pulse which functions as the clock generator output. This compare pulse is also fed back to the reset terminal of register 12, changing the number stored in the register to the output of adder 20.