Browse Prior Art Database

Selective Planarization Process and Structures

IP.com Disclosure Number: IPCOM000043775D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Bennett, RS Nastasi, V Silvestri, VJ Tang, DD [+details]

Abstract

A non-critical reactive ion etch (RIE) etch-back step is used to simply expose polysilicon present on horizontal surfaces such that subsequent removal of the polysilicon can be accomplished through a simple wet or dry selective etch. The significant problem which is solved using this technique is the elimination of need for complicated back polishing techniques employing RIE and chemical mechanical polishing to remove the silicon on the horizontal oxide surfaces. The major structures and general process discussed in this article are shown in Figs. 1-6. The general intent of the structures and process is to form or deposit a material 14 in a recess (e.g., a trench) formed in a semiconductor 10, such as silicon, as shown in the figures and then to protect this material 14 with another material 15, e.g.