Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
The driver circuit translates a +.3V to 1.7V signal swing at the input to a -2.0V to -.8V signal swing at the output. The circuit may be employed as an interface in the communication between internal chip voltage levels and voltage levels external to the chip. The circuit operates as a NAND gate. Putting either driver input "A" or "G" at a logical "0" (+.3V) turns TX1 on, forcing node "B" to +.45V which turns TX2 off. Thus, node "C" rises to approximately +1.6V. TX3 and TX4 are always on due to the load which they are driving. The voltage divider, formed by R4 and R5, causes the voltage across R4 to be equal to one VBE drop. Thus, the voltage at node "F" is equal to three VBE drops plus the +1.6V at node "C", giving the required up level of -.8V. With all the inputs at a logical "1" (A,G=+1.