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Mutli-Line Fault-Tolerant Communications Adapter

IP.com Disclosure Number: IPCOM000043839D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Johnson, WJ Millas, RJ Weakley, TL [+details]

Abstract

A technique is described whereby a multi-line fault-tolerant communications adapter is used to increase the reliability of communication systems. The multi-line fault-tolerant communications adapter concept, as shown in the drawing, interconnects the communication line multiplexer of each USART (Universal Synchronous/Asynchronous Receiver/Transmitter) to the main Central Processing Unit (CPU). Should a fault occur in any one of the microprocessor subsystems (microprocessor, RAM (Random-Access Memory), ROM (Read-Only Memory) or bus), the system will search for a free microprocessor subsystem, or a subsystem with a lower priority than the failing subsystem. The line multiplexer will then channel the line to the free or lower prioritized subsystem.