Browse Prior Art Database

Dual FIFO Dynamic RAM Manager for a Buffer Insertion Ring

IP.com Disclosure Number: IPCOM000043842D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Johnson, WJ Maxwell, HM Millas, RJ Weakley, TL [+details]

Abstract

A technique is described to improve memory management local network architecture by utilizing dual FIFO (first-in first-out) buffers. Memory management, when used in a high-speed communications network switching architecture, such as a buffer-insertion ring-type architecture, must provide the following conditions: 1. Variable message length for received messages; 2. Track the beginning and ending addresses of variable message lengths to determine byte count; 3. Dynamically assign RAM (Random Access Memory) allocation for efficient utilization of microprocessors and I/O (Input/Output) devices; and 4. Dynamically allocate RAM segments for transmission of messages.