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Browse Prior Art Database

FET Logical Analysis Program

IP.com Disclosure Number: IPCOM000043845D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Ditlow, G Donath, WE Ruehli, AE [+details]

Abstract

This article describes a method for computing the H1, H0, S1, and S0 function of complex FET circuitry embodied in an APL implementation which generates these functions for one output of a 32-bit barrel shifter in about a minute of computation time. This device had in excess of 384 transistors. The figure shows the FET network of an 8-bit barrel shifter. The functions for output F0 are: (Image Omitted) Note that simultaneous time on S1P and S1N opens a larger number of paths - the same for S2P and S2N. The algorithm described herein works recursively. At each step, it assigns a value to just one input variable of the network, and may decide that several edges and/or assignments of variables need not be considered at deeper levels of recursion.