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Densely Arrayed EPROM Having Low-Voltage Write and Erase

IP.com Disclosure Number: IPCOM000043851D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Adler, E [+details]

Abstract

This erasable EPROM (electrically programmable read-only memory) has an array of FET memory cells of the two-device NOR circuit type in which both writing and erasing functions are accomplished by means of a polysilicon floating-gate tunnel-effect technology that uses low power and eliminates many diffusion coupling areas which otherwise would limit cell density rather severely in this type of array. Fig. 1 shows the type of circuitry used in this array. Each memory cell is a two-device NOR circuit containing a floating-gate FET associated with an access FET, as indicated. The figure shows four of these cells arranged respectively at the crossings of two bit lines B10 and BL1 with two word lines, each word line comprising a control gate line CG0 or CG1 and an associated read select line S10 or SL1.