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Circuit for a Self-Gating Timing Chain in a Semiconductor Memory

IP.com Disclosure Number: IPCOM000043857D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

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Baier, E Loehlein, WD Mueller, R [+details]


A scheme and a circuit arrangement are described for a self-gating timing chain in a semiconductor memory, which provide for the internal row array select (RAS) phase to be used to start an enabled column array select (CAS) timing chain. Present semiconductor memories, particularly FET (field-effect transistor) memories, use select schemes with several select phases that have to be timed very carefully. Faulty timing, however slight, may lead to memory chip failure. To remedy this, an interlocking RAS/CAS scheme is described that eliminates critical timing edges in semiconductor memory address systems. Particularly in dynamic memories, the addresses are often multiplexed between the rows and columns. This necessitates that address switching be effected between RAS and CAS signals. Fig.