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Browse Prior Art Database

Reducing AGI in Split Cache Processors

IP.com Disclosure Number: IPCOM000043868D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Pomerene, JH Puzak, TR Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

The Address Generate Interlock (AGI) associated with consecutive instructions of split cache processors can be reduced by creating an Address Generate History Table (AGHT) which contains instruction addresses and the operand address needed to relieve the AGI. Table entries are made when AGI occurs and are accessed by prefetching activity. Each taken branch that is followed by an AGI causes an entry to be made in the AGHT. The processor sends its taken branch I-fetches to both the I-cache and the D-cache directory. The AGHT within the D-cache directory, recognizing the I-fetch, causes the normal action of the directory to be superseded by an action which finds the associated D-access-address required and returns this to the directory to perform the prefetch.