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# Differential Logic Delay Representation in a Single-Ended Software Simulation System

IP.com Disclosure Number: IPCOM000043877D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 34K

IBM

## Related People

Leininger, JC: AUTHOR [+1]

## Abstract

A technique is described to provide for logic simulation and complementary output levels in differential cascode current switch circuits when differences in transistor logic delays occur in the complementary outputs. Differential Cascode Current Switch (DCCS) circuits operate at relative levels of two complementary input signals and two output levels that may switch at different times. Since DCCS circuits do not effectively switch electrically until the high and low input signals change relative to each other, the propagation delay for the circuit may vary, depending on which input signal pair was changed. In the DCCS circuit, as shown in Fig. 1, if all the inputs A to E are positive, a simultaneous change in the inputs E and E will cause both outputs Q and Q to switch at the same time.

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Differential Logic Delay Representation in a Single-Ended Software Simulation System

A technique is described to provide for logic simulation and complementary output levels in differential cascode current switch circuits when differences in transistor logic delays occur in the complementary outputs. Differential Cascode Current Switch (DCCS) circuits operate at relative levels of two complementary input signals and two output levels that may switch at different times. Since DCCS circuits do not effectively switch electrically until the high and low input signals change relative to each other, the propagation delay for the circuit may vary, depending on which input signal pair was changed. In the DCCS circuit, as shown in Fig. 1, if all the inputs A to E are positive, a simultaneous change in the inputs E and E will cause both outputs Q and Q to switch at the same time. If the turn-on and turn-off delays are equal, the output levels will change at the same time, as shown in the Fig. 2 timing diagram, and the simulation programs will show the accurate circuit representation. When the A and A levels change as compared to E and E in Fig. 1, four extra transistor delays are introduced in the Q as compared to the Q path. This causes the output levels Q and Q to change at different times in simulation when each transistor is assigned a delay. This causes single-ended simulation systems to detect the value of Q and Q to be at the same levels during portions of the simul...