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Write Improvement Scheme for Harper Cell in Low Power Supplies

IP.com Disclosure Number: IPCOM000043899D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Wang, WY [+details]

Abstract

The circuit schematic shown above illustrates a write improvement scheme for a low power memory using a Harper cell which utilizes a switched bit write current to ensure fast and reliable read and write operation. This technique contrasts with the prior art where equal current sources (IREAD) are conventionally connected to both left(L) and right(R) bit lines, the same value of current serving both read and write cycles. In the scheme here disclosed, a current switch circuit switches more current(IWRITE) into one side of the bit line pair in order to speed up the fall time of the bit line voltage, thereby decreasing the time to write the Harper cell to opposite data polarity. When the Harper cell is selected, write operation is initiated from read/write control and data input circuits.