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Non-Sequential High-Performance Processing Disclosure Number: IPCOM000043905D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

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Capozzi, AJ Kelley, WJ Wassel, ER [+details]


A process to reduce execution delay in a high performance processor is accomplished by pre-analyzing interdependencies and allowing for maximum parallel execution of instructions. This processor design uses information, relating to instruction input requirements, to control multiple instruction execution, thereby maximizing overall processor performance. The instruction buffer, which normally holds pre-fetched instructions, is replaced by an Instruction Cross Reference Array (IXA) 11 containing not only the decoded instruction 12 but instruction execution status 18, operand information 14, 15 needed to determine when execution can be started, and an operand input/output (I/O) area 19. As instructions are fetched from storage 13, they are decoded and the information is placed in the IXA fields 12, 14, 15, 18.