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Fault Simulation for Pass Transistor Circuits Using Logic Simulation Machines

IP.com Disclosure Number: IPCOM000043916D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Barzilai, Z Silberman, GM Tang, DT Woo, LS [+details]

Abstract

An efficient fault simulation procedure for pass transistor circuits using logic simulation machines is described below. Existing fault models for use at the gate-equivalent level have proven to be inadequate for accurate pass transistor simulation [1,2]. The main reasons for this are the special features present in pass transistor circuits, i.e., bidirectionality, memory states and sneak paths. Another major inconvenience with gate-equivalent modelling is the lack of physical equivalence between the model and the actual circuit, therefore making it more difficult to evaluate significant faults. On the other hand, accurate, circuit level simulation (e.g., SPICE [3]) is too costly and time consuming. Based on the ideas presented in [4], i.e.