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Distributed Error Checking/Correcting Scheme for Distributed Cache Memory Systems

IP.com Disclosure Number: IPCOM000043940D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Gheewala, TR Kronstadt, EP [+details]

Abstract

A method is provided which accomplishes single error correction and double error detection per word by using an orthogonal parity checking scheme. Row parity checking is done on the DRAM (dynamic random-access memory) chips and column parity checking is done on the memory controller chip. The idea behind distributed error checking/correction (DECC) is that the bits in the row buffer are only partially checked in the DRAM, with the remainder of the checking done via byte parity on the data words read from a memory bank consisting of nine DRAM chips. DECC distributes the parity check/generation logic between the DRAM chips 11 and a memory control chip 12. This logic is also distributed, to some extent, over time.