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Line Crossing Branch Prefetch Buffer Disclosure Number: IPCOM000043965D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

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Pomerene, JH Puzak, TR Rechtschaffen, RN Sparacio, FJ [+details]


An I-shadow, defined as a secondary cache directory, when enhanced to include the full address (as contrasted with the line address), provides a processor an instruction buffer prefetch opportunity. An I-buffer is reserved within the decoder and is prefetched into, based on the address of the next line that is contained within the I-shadow. The decoder detects a branch which is: (a) guessed taken, (b) goes out-of-the-current line. The line-crossing-prefetch-buffer is checked to determine if it contains the target of the taken branch. When it does, the taken branch delay is avoided. The advantage of this approach over a simple branch history table is that there is no penalty for incorrect prefetch/ guessing, assuming the I-fetch bandwidth exists.