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Opcode Trap for Diagnosis of Logic Faults

IP.com Disclosure Number: IPCOM000044029D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

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Related People

Feeney, JW Spearman, RW [+details]


A technique for the detection of logic faults consists of using signature analysis to determine if a failure has occurred. Because a signature has failed is usually not sufficient to diagnose the cause of the failure. Additional information can be acquired by looking at the states of the logic pins, that make up the signature, at the time the failure is detected. This technique is being used to detect faults in logic designs that contain some intelligence, such as a microprocessor, and that execute programs which test themselves and create the signature. The Opcode Trap is a method of collecting additional information in order to diagnose faults occurring in these cases. Each instruction operation code is collected as it is executed and stored in a buffer until the next instruction begins execution.