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LSSD Clock Insertion Method for Reducing Test Time

IP.com Disclosure Number: IPCOM000044054D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Bouldin, EA Guzowski, TS [+details]

Abstract

Level sensitive scan design (LSSD) tests (called tester loops) are normally comprised of five or more actions where each action consists of one or more stimulus patterns. This standard LSSD format, as shown in the flow chart, may be selectively altered by a process of pattern insertion, i.e., by adding patterns to the body of the tester loops. Clock insertion is a special case of pattern insertion characterized by adding patterns which are generally LSSD clock pairs (e.g., A-clock/B-clock, or C-clock/B-clock). The clock-insertion method modifies selected test sequences from an existing test set to improve their fault detection efficiency, thereby making it possible to completely eliminate other test sequences. The clock-insertion method begins with an analysis step that determines the number of faults caught in each tester loop.