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Apparatus Including Shift Register Latches Which Allows Performance Evaluation

IP.com Disclosure Number: IPCOM000044061D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Van Horn, J [+details]

Abstract

This article describes a hardware technique where the shift register latches (SRLs) of any level sensitive scan design (LSSD) designed chip can be configured (due to innovative test hardware) so that they effectively become a ring oscillator. The period of oscillation will be the propagation delay through the LSSD latches. This propagation delay measurement can then be used to characterize the electrical performance of the chip. Test hardware designs are presently available which accurately measure oscillator periods. The novelty of this disclosure is the fact that the SCAN-OUT pin 11 is tied back to the SCAN-IN pin 12 via an inverter 13 utilizing test hardware 14. Inverter 13 can be switched out of the circuit via relay 15 if the SCAN-OUT off-chip driver (OCD) is an inverting OCD.