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Avoidance of Power Supply Sequencing at Chip Power-On Time

IP.com Disclosure Number: IPCOM000044093D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Legrand, B Nuez, JP [+details]

Abstract

This proposal is to be used in any chip requiring two power supplies V1 and V2, with V2 higher than V1, and allows the power supplies to be switched ON in any order. In a chip where there are two power supplies V1 and V2 in resistor beds, the high supply V2 has to be applied before V1 in order to prevent a damaging current from flowing from the V1 power supply to V2 power supply during a few milliseconds. In a device such as that shown in Fig. 1, this occurs when a resistor is biased to V1 and the N epi contact to V2. When V1 is applied first, a current flows between the V1 biased resistor port and the N epi-contact, since the junction P base N epi is forward biased. To prevent this from happening, the reach through of the N epi contact is removed, as shown in Fig. 2.