Dual-Mode Address Relocate System
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
A data processing system is provided with single address relocate structure which efficiently operates in a zero-origin non-VM (virtual memory) relocate mode and a full VM mode. Facilities are included to support: 1) 4K byte fixed page size, 2) memory protection, 3) bypass of an address translate function, and 4) page access and write reference detection. With reference to the drawing, the relocate structure includes a fast random-access memory 10. The size of memory 10 is 4K by 4 bytes (8 bits per byte). Memory 10 functions as an address translation table having the fields shown in the drawing.