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Densely Arrayed EEPROM Having Low-Voltage Tunnel Write

IP.com Disclosure Number: IPCOM000044125D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Adler, E [+details]

Abstract

A combination of semiconductor device fabrication techniques is employed to construct an electrically erasable and programmable read-only memory (EEPROM) in which the memory cells are polysilicon floating-gate MOSFETs arranged serially in blocks of AND-type circuitry. The oxide insulation on the floating gates can be readily tunneled by low write voltage to charge these gates for bit storage. Groups of serially connected memory cells form AND circuits in word blocks that require relatively few points of electrical contact between the cells and the drive lines. This arrangement permits dense positioning of the memory cells and low-power operation of the array. Fig. 1 shows on a simplified scale the general format of the EEPROM circuitry.