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Selective Substrate Biasing for CMOS Circuits

IP.com Disclosure Number: IPCOM000044140D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Rideout, VL Wissel, L [+details]

Abstract

Selective substrate biasing for complementary metal oxide semiconductor (CMOS) circuits locally optimizes performance and density. CMOS devices at chip I/O points are given substrate bias for latch-up protection, while the chip interior is layed out at higher density without substrate wiring. In CMOS technology, the n-channel/p-channel device transconductance mismatch is such that the emphasis is placed on n-channel devices for performance optimization. Accordingly, it is n-channel devices that are given a substrate bias to improve their characteristics (junction capacitance, threshold control). This substrate bias has the additional advantage of providing latch-up protection by preventing n-channel I/O devices from becoming forward biased.