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Buffered Logic Disclosure Number: IPCOM000044163D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

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Erdelyi, CK [+details]


This article describes a metal oxide semiconductor field-effect transistor (MOSFET) logic circuit which provides power-performance and density improvement over conventional N-channel metal oxide semiconductor (NMOS) and complementary metal oxide semiconductor (CMOS) logic circuits. Complex logic functions are generated using a low level power supply VP1. Sensing and driving functions use a high FET-level power supply VP. Fig. 1 shows the block diagram of the invention. The complex logic stage 11 performs the logical function utilizing low voltage swings and power as well as small FET devices. The sense amplifier 12 detects the change of state in the logic and converts it into a valid logic level change.