Browse Prior Art Database

Method for Forming Laterally Graded Fet Junctions

IP.com Disclosure Number: IPCOM000044184D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
El-Kareh, B Noble, WP [+details]

Abstract

This article describes of method of fabricating shallow graded junctions with a highly doped region for the purpose of low sheet resistance and a lightly doped graded shallow extension toward the device channel (which determines the device properties). This extension can be made both shallow and lightly doped to reduce undesirable multiplication of leakage current to substrate and hot electron threshold voltage instability. The method of fabrication is as follows: 1. Use the conventional silicon gate process up through deposition and definition of the polysilicon gate 11, as shown in Fig. 1. Deposit a layer 12 of chemical vapor deposition (CVD) arsenic-doped oxide to a thickness of the desired junction extension (Fig. 2). 2.