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Substrate Voltage, Bump Test for Dynamic RAM Memory Devices

IP.com Disclosure Number: IPCOM000044197D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Nack, P Panagiotopoulos, G [+details]

Abstract

A substrate voltage, bump test for dynamic random-access memory (RAM) devices is a method for testing the signal margin under manufacturing conditions without the excessive test time of complex patterns used to stress the cell signal margin. Thus, the substrate voltage can be used to incouple or outcouple voltage to the storage cell. This new technique makes use of these "characteristics" by writing and reading the cell at different substrate voltages. First, the cell is written with a given substrate voltage, then the substrate voltage is changed and the cell is read. A negative substrate voltage jump (for example, -1.4 V to -2.4 V) is outcoupling a voltage such that the high ("1") level margin of the signal is diminished (Fig. 1). A positive substrate voltage jump (for example, -2.4 V to -1.