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Patchable Read-Only Storage and Other Patchable Functions

IP.com Disclosure Number: IPCOM000044210D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue


Related People

Bertin, CL Bush, GH Kalter, HL [+details]


A memory architecture is described in which an alterable PLA (programmable logic array) and a ROS (read-only storage) or a RAM (random-access memory) have inputs and outputs which are connected in parallel. The parallel connection allows the PLA to inhibit memory data at a given address in either the ROS or the RAM, while providing user-edited data for the given address in ROS or RAM. The use of a PLA in this manner eliminates the need for changes in the microcode as a result of errors in either ROS or RAM. These microcode changes usually require the use of PROM (programmable read-only memory) or EEROM patch cards which are very expensive on a per bit basis and also inconvenient to install. The ROS patch feature is included directly on the ROS chip and is in parallel with the ROS functions.