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Method for the Formation of an FET Depletion-Mode Load Device With a Buried Contact Disclosure Number: IPCOM000044222D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

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Fredericks, EC Kotecha, HN Stanasolovich, D [+details]


A sequence of figures is shown illustrating the process for the formation of an FET (field-effect transistor) depletion-mode load device with a buried contact. Fig. 1 shows a first stage of the process invention, which starts with the recessed oxide layers 4 and 4' having already been formed on the surface of the silicon substrate 2 of P-type conductivity, thereby defining a device region 1. A layer of thin gate oxide 6 is formed on the surface of the silicon substrate between the recessed oxide regions 4 and 4'. A layer of photoresist 8 is uniformly deposited over all exposed surfaces of the assembly. The process for patterning the photoresist layer is to include exposure by an electron beam.