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High Efficiency Wrap Test Circuit

IP.com Disclosure Number: IPCOM000044248D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Leotard, R Montanari, G [+details]

Abstract

The circuit shown in the drawings allows a wrap test at the modem end cable to be performed at operational speed with full effectiveness. In the interface shown in Fig. 1, between a data terminal equipment (DTE) and a data communication equipment (DCE) the wrap test is performed by connecting the Transmit Data driver to the Received Data receiver, the Data Terminal Ready (DTR) driver to the Data Set Ready (DSR) receiver, and the Request to Send (RTS) driver to the Ready for Sending (RFS) and Received Line Signal Detector (RLSD) receivers through a Wrap Switch. Drivers and receivers are referenced by DRV and REC, respectively. A logic circuit 1, shown in Fig. 2, is provided to allow the test of the receive clock and the clock receiver 4 (Fig. 2) to be performed.