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Self-Aligned Field Isolation Process for Cmos-Fets

IP.com Disclosure Number: IPCOM000044261D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05

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Dash, S Mohler, RL [+details]


This article describes a process which fabricates an N-well complementary metal oxide semiconductor (CMOS) with a self-aligned field isolation implant while protecting the wafer with a layer of nitride during the N-well drive-in step. Fig. 1 shows a standard semirecessed pad oxide (SROX) 11/pad nitride 12 structure with an additional low pressure chemical vapor deposition (LPCVD) SiO2 layer 13 of suitable thickness (e.g., 2500 ˜ to 3500 ˜). Fig. 2 shows the structure after the N-well regions have been exposed with a lift-off resist 14 profile and an N type species 15 (e.g., phosphorus) has been implanted through the pad oxide/nitride/ oxide stack 11, 12, 13 at a suitable energy to provide the desired N-well 16 doping profile. Fig.