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Scheme to Achieve Even Cache Utilization in Engineering and Scientific Computation Disclosure Number: IPCOM000044283D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Agarwal, R Hawrot, DP Stein, DM [+details]


A cache to be filled with array elements having a stride of N bytes is accomplished in the following mapping scheme. Currently used cache mapping schemes map main memory lines to cache modulo P (a power of 2, for example, 128). If N is an even multiple of line size (LS), the currently used cache line mapping scheme results in a great deal of cache interference because N/LS is not relatively prime to P; thus, only a portion of the cache gets utilized. A scheme is designed which reduces the cache miss ratio and achieves even cache utilization by mapping main memory lines to cache modulo P, where P is a prime, thus maintaining cache interference at a minimum. The following is a practical scheme using P=127: 1. Remove, from the address, the last Log2LS bits which indicate the byte location within a line. 2.