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LSSD Clock Generation Circuit

IP.com Disclosure Number: IPCOM000044298D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Welbon, EH [+details]


A technique is described whereby a master oscillator, used as an input, produces a two-phase level sensitive scan design (LSSD) clock as an output to microprocessors. The key feature of this clock generation circuit is that it generates the alternate clock's phases with a guaranteed off-time between phases. The guaranteed off-time is one half of the period of the master clock and, therefore, is reliably controlled. Applications often require microprocessors to have two clock inputs, as shown in the timing diagram (Fig. 1). The circuit, as shown in Fig. 2, is self-initializing and runs on a clock from master oscillator 10. Further, the circuit can provide simple synchronization of two microprocessors. This is done by using the dead points in the output clocks to clock interprocessor interface latches.